DESIGN OF LOW POWER FULL ADDER CIRCUIT USING ADIABATIC LOGIC

Abstract

Due to the increasing demand in mobile electronic devices, power efficient VLSI circuits are required. Computations in the devices need to be performed using low power circuits operating at greater speed. Addition is the most basic arithmetic operation and adder is the most fundamental arithmetic component of the processor. Adders are the key building  blocks in arithmetic and logic units and hence increasing their speed and reducing their power consumption strongly affects the speed and power consumption of processor. Ripple carry adder achieves less area and high speed for many data processing processors to perform fast arithmetic functions. In many computational systems the delay and power consumption problem is eliminated by using low power consumption methods. Mostly CMOS technology is used to design low power digital circuits. Adiabatic logic circuits offer significant reduction in power dissipation when compared with static CMOS. Adiabatic switching logic conserves the energy instead of heat dissipation. The functionality and performance analysis is carried out using Tanner EDA tool.